This invention relates to an image memory.
As memories suitable for high speed data processing in engineering work stations (EWSs) or computer graphics (CG), etc. and display thereof, attention in recent years is being drawn to dual port video RAMs (hereinafter referred to as DPRAMs). Such DPRAMs are provided with a random access port (hereinafter referred to as a RAM port) including a memory array accessible at random (e.g., a DRAM), and a serial access port (hereinafter referred to as a SAM port) including a serial access memory cyclically and serially accessed asynchronously with the RAM port. In such DPRAMs, since transfer of data is made between the RAM port and the SAM port, it is necessary that the timing at the RAM port and the timing at the SAM port should be made synchronous with each other only at the time of this transfer cycle. The timings in this transfer cycle will be described with reference to FIGS. 6A and 6B. In the case of data transfer of a certain row R of a memory array 1 of the RAM port to a serial access memory 2 of the SAM port which is incessantly making a serial access (see FIG. 6A), a procedure is taken to make first external signal DT for controlling transfer (see time T.sub.1 of FIG. 6B) fall. If the external signal DT is at "L" level at the time when the signal RAS falls, the operational mode enters the transfer cycle.
In this transfer cycle, in the same manner as that in an ordinary RAM cycle, a row address and a column address are given synchronously with falls of RAS and CAS (see times T.sub.2 and T.sub.3 of FIG. 6B), respectively. Unlike from the ordinary RAM cycle, the row address indicates a row of the memory array 1 to be transferred, and the column address indicates a TAP address serving as a position initiating a new serial cycle after completion of transfer. From the next serial cycle (see time T.sub.6 of FIG. 6B) when the external signal DT has risen, transferred data is outputted with the TAP address being as a leading address. It is necessary that the rise timing (time T.sub.5) of the external signal DT should be given for a time period from the rise (time t.sub.4) of the serial clock signal SC to the next rise thereof (time t.sub.6). Accordingly, there are a restrictions in the time intervals t.sub.1 (=T.sub.5 -T.sub.4) and t.sub.2 (=T.sub.6 -T.sub.5). Furthermore, since the cycle time of the serial clock signal SC is 30 to 40 nsec, restrictions on the time intervals t.sub.1 and t.sub.2 are severe in application. To relax this, a split transfer system has been proposed.
This system is briefly described in NIKKEI ELECTRONICS No. 431, p. 126, Oct. 5, 1987.
This split transfer system will be described with reference to FIGS. 7A and 7B. The serial access memory 2 of the SAM port in which the split transfer system is used is split or divided into two sections of SAM (L) and SAM (U) as shown in FIG. 7A. These split SAM (L) and SAM (U) correspond to "0" and "1" of the most significant bit (hereinafter referred to as MSB) of the TAP address, respectively. Thus, independent data transfer can be made, respectively. Now will be considered the case where a transfer cycle takes place when SAM (L) is subjected to serial access to carry out transfer of the row R of the memory array 1 of the RAM port. In the same manner as in the case of FIG. 6A, the row address indicates the row R. MSB of the TAP address is disregarded and is set to MSB ("1" in this case) on the side where no serial access is conducted.
In this case, the SAM (U) on the side of the set MSB carries out the transfer operation. The transferred data is accessed from a TAP address where MSB is newly set when serial access advances to shift from SAM (L) to SAM (U). In the case shown in FIGS. 7A and 7B, when a transfer cycle takes place for a time period of the serial addresses 0 to 127, the serial addresses 128 to 255 are subjected to transferring operation from the portion corresponding to the row R. When the serial access advances to 127 to enter the next SC cycle, TAP address is accessed. Serial access is therefore continued further. As stated above, the split serial access memory section where serial access is carried out and the split serial access memory section where transfer is carried out are different from each other, and an address of the preceding cycle where an access to the TAP address is made is predetermined. Accordingly, restriction on the timings as in the case of FIGS. 6A and 6B does not exist.
Consideration will now be made in connection with the method of constituting a data buffer for implementing high speed processing to display picture data using such a split transfer system.
As a random access memory of DPRAM, a DRAM is used. For this reason, by using the page mode of DRAM, it is possible to access data of the same row in a time one half to one third of a time in the case where the row address changes. Further, data of one row corresponds to data serially outputted from the SAM section, and the serial data serves as pixel data of a picture displayed. Therefore, how these pixels are arranged as a picture is important for high speed picture processing. From a viewpoint of processing of picture, an employment of the method capable of processing, at a high speed, pixels in areas close to a square as far as possible permits a high speed processing for any image pattern processing. Namely, high speed picture processing can be made in any direction of longitudinal, lateral, or oblique direction. Thus, how data of one row which can be accessed in the page mode are allocated in a longitudinal direction with respect to the scanning direction of a picture displayed becomes important.
The case where a picture is composed of an array including four DPRAMs in a scanning direction and four DPRAMs in a longitudinal direction, i.e., an array of 4.times.4 is employed as a tile, will now be considered.
FIGS. 8A and 8B show the case where there is employed a DPRAM of the split transfer system having data of one row of 256 bits and the depth of a serial access memory (hereinafter referred to as a SAM) of 256 bits. Further, the picture size is assumed to be 1536 pixels in a scanning direction for brevity of explanation. In FIG. 8A, R0, R1, R2, . . . represent rows of a random access memory (hereinafter referred to as a RAM), respectively. L of 0 to 127 and U of 128 to 255 in the column direction represent columns where data are transferred to bisected SAMs in the split transfer, respectively. Since the section in the scanning direction is composed of four devices M.sub.1, M.sub.2, M.sub.3, and M.sub.4, 1536 pixels in the scanning direction correspond to data corresponding to three split segmented SAM (=1536/(4.times.128)). Accordingly, when L and U of the segmented SAMs are allocated to pixels in a longitudinal direction, it is possible to conduct picture processing of an area closer to a square by an access in a page mode of one row. Namely, data of the RAM section are subjected to a split transfer in order of R0L, R1U, R2L, R0U, R1L, R2U, . . . Since data are serially outputted from the SAM section to scan pixels, the configuration of data as a picture is such that the area indicated by slanting lines of FIG. 8B is composed of data of the row R0. This area can be subjected to an access of any portion in the page mode. Accordingly, the picture is covered with tiles of slanting lines shown in FIG. 8B such that it can be accessed in the page mode. Thus, high speed picture processing can be conducted.
Further, more detailed consideration of the data configuration in the scanning direction will now be made. How pixels are constructed from serial data of four DPRAMs is shown in FIGS. 9A and 9B. Data from the SAM 2 of the devices M1 to M4 are subjected to parallel-to-serial conversion as shown in FIG. 9A, and are outputted as serial data to constitute pixels one by one. Thus, it is sufficient to make a serial access from SAM 2 at a speed one fourth that of the serial out for display of picture, thus making it possible to lessen the load on the SAM 2. Pixel data when such a parallel-to-serial conversion is carried out, are repeated in sequence as data from the DPRAM of M1, M2, M3, and M4 in order (see FIG. 9B). The frame of R0L, etc. of the title which has been described with reference to FIG. 8B is of such a data structure.
Let now consider the case where the picture size is different from that in the above-described case. The case where the number of pixels in a scanning direction is 1024 is shown in FIGS. 12A and 12B. When it is assumed that the size of a tile used is 4.times.4 in the same manner as that in the above-described case, 1024 pixels correspond to the two segmented SAM sections (=1024/(4.times.128)).
At this time, in order that L and U of split data of one row are caused to correspond to the pixel arrangement in a longitudinal direction, it is necessary to carry out a split transfer in order as shown in FIG. 10A. Namely, when transfer is carried out in order of R0L, R1U, R0U, R1L, . . . , the area indicated by slanting lines in FIG. 10B can be desirably accessed in the page mode. However, in the case of transfer at this time, L and U cross each other with respect to SAM. Accordingly, such a transfer cannot be carried out by a conventional DPRAM.
Naturally, when the size of the tile is changed, a buffer can be constructed even by this picture size without cross transfer. However, the design of the buffer memory system must be changed for every picture size displayed. Further, since a cross transfer occurs unless the number of tiles in a scanning direction is necessarily odd as seen from the case of FIG. 8B, it cannot be necessarily said to select an optimum tile size of a memory capacity which is not wasteful with respect to a picture size.